随着图像处理和大数据等技术的飞速发展，数据量呈爆发式增长，这使得数据中心对存储性能的需求日益加剧。传统的内存技术存在着扩展困难、动态能耗高等问题，无法满足海量数据存储需求。具备按字节寻址、能耗低、读写延迟低、非易失以及扩展性良好等优势的新型非易失型存储器（Non-volatile Memory，NVM）逐渐开始被国内外广泛研究，并有望替代传统内存。然而，由于物理结构的限制，NVM的写入次数有限、写延迟较高，难以应用于大规模数据存储。

为了提升写入带宽并增加存储空间，数据通常以压缩的形式存储于内存中。然而，在压缩存储场景下，NVM的存储有效性和寿命面临三大挑战。首先，由于压缩算法将大块数据压缩后集中存储在前半部分，导致内存块的局部磨损问题。目前缺乏有效指标来刻画这种局部磨损对NVM寿命的影响；其次，局部磨损会导致NVM块内磨损不均问题，进而缩短其寿命。最后，当前压缩算法较多，其对NVM局部磨损程度有所差异，需要在不同工作负载场景下做出有效选择。

针对以上三个问题，本文的主要创新点和研究内容总结如下：

提出衡量局部磨损的指标。为了刻画局部磨损对NVM块寿命的影响，本文提出了一个新的衡量指标——局部位翻转，用来描述压缩算法对NVM内存块在局部区域产生的位翻转数量，进而得到其对NVM寿命的影响。

提出压缩场景下的块内磨损均衡算法。为了解决压缩算法带来严重的局部磨损的问题，本文提出了一种滑动写入（Sliding Writes，SlidW）的块内磨损均衡机制。SlidW将一个内存块分为若干个相同大小的区域，并根据新写入数据的大小、剩余空间和其他辅助信息，将写入的数据位置分为五种状态。根据判定的写入状态，将压缩后的数据分布到整个内存块的区域中，以避免数据集中在某个区域中。实验结果表明，使用SlidW算法能够减少23.61%的局部磨损，增加59.07%的NVM寿命。同时，SlidW对读写延迟和能耗消耗的影响极小，可忽略不计。

提出基于数据采样的自适应NVM压缩算法。针对不同工作负载下压缩算法的磨损程度差异问题，本文提出了一种基于数据采样的自适应NVM压缩算法。该算法分为特征采样和压缩实施两个阶段进行。在特征采样阶段，对三种常用的压缩算法的压缩率和位翻转情况进行统计，并根据该结果选择合适的压缩算法。在压缩实施阶段，根据选择的压缩算法配合SlidW算法进行数据写入操作。实验结果表明，相比主流的压缩算法而言，自适应压缩算法能减少平均40%的局部磨损，并增加平均45%的寿命。

本文提出的方法能够极大改善压缩场景下的NVM寿命，以推动NVM在海量数据存储场景下的广泛应用和市场竞争力。

[1] 蔡涛, 王飞, 马跃明, 等. 面向DNN的高并发NVM文件系统[J/OL]. [2023-03-09]. https://doi.org/10.20009/j.cnki.21-1106/TP.2022-0037.

[2] 祝贺, 华强胜, 金海, 等. LMSA:NVM环境下高性能动态图处理数据结构[J]. 计算机学报, 2022, 45(07): 1446-1461.

[3] 环球科学. 我们究竟产生了多少数据? [EB/OL]. [2023-03-09]. https://huanqiukexue.com/a/qianyan/xinxi__nenyuan/2021/0528/31624.html.

[4] 前瞻产业研究院. 2020年中国大数据产业市场发展现状分析：2025年全球数据量将达163ZB大数据安全立法进程加速[EB/OL]. [2023-03-09]. https://www.qianzhan.com/analyst/detail/220/200320-6e0eb0c1.html.

[5] Akansh Agarwal. BIG DATA - IMPACT IN INDIA AND ON OTHER BIG GIANTS[EB/OL]. [2022-04-11]. https://www.linkedin.com/pulse/big-data-impact-india-other-giants-akansh-agarwal.

[6] 百度文库. DRAM技术发展史年表[EB/OL]. [2023.03.26]. https://wenku.baidu.com/view/4716dce287254b35eefdc8d376eeaeaad1f3161a.html?_wkts_=1679913944645&bdQuery=dram的集成发展.

[7] 全球半导体观察. 平面→立体，3D DRAM重定存储器游戏规则[EB/OL]. [2023.03.26]. https://www.163.com/dy/article/I09DA6A405199TU1.html.

[8] Boukhobza J, Rubini S, Chen R, et al. Emerging NVM: A Survey on Architectural Integration and Research Challenges[J]. Acm Transactions on Design Automation of Electronic Systems, 2018, 9(2): 1-32.

[9] Pekhimenko G, Seshadri V, Kim Y, et al. Linearly compressed pages: A low-complexity, low-latency main memory compression framework[C]//Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture. 2013: 172-184.

[10] Xu J, Feng D, Hua Y, et al. Extending the lifetime of NVMs with compression[C]//2018 Design, Automation & Test in Europe Conference & Exhibition. IEEE, 2018: 1604-1609.

[11] Feng D, Xu J, Hua Y, et al. A low-overhead encoding scheme to extend the lifetime of nonvolatile memories[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, 39(10): 2516-2529.

[12] Jadidi A, Arjomand M, Tavana M K, et al. Exploring the Potential for Collaborative Data Compression and Hard-Error Tolerance in PCM Memories[C]// IEEE/IFIP International Conference on Dependable Systems & Networks. IEEE, 2017: 85–96.

[13] Jadidi A, Kandemir M, Das C. Tolerating Write Disturbance Errors in PCM: Experimental Characterization, Analysis, and Mechanisms[C]// 2018 IEEE 26th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems. IEEE Computer Society, 2018: 53–65.

[14] Escuin C, Ibáñez P, Navarro D, et al. L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime[J]. Plos one, 2023, 18(2): 1-36.

[15] Priya B K. Enhancing the lifetime of STT-RAM using compression based wear leveling technique[J]. Microelectronics Reliability, 2023, 143: 114939.

[16] Chen Z Y, Hua Y, Zuo P F. Approximate Similarity-Aware Compression for Non-Volatile Main Memory[J]. 2023: 1-19.

[17] Upadhyay S, Nath A, Kapoor H. Exploiting successive identical words and differences with dynamic bases for effective compression in Non-Volatile Memories[C]//Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design. 2022: 1-6.

[18] Rashidi S, Jalili M, Sarbazi-Azad H. A Survey on PCM Lifetime Enhancement Schemes[J]. ACM Computing Surveys, 2019, 52(4): 1-38.

[19] Xia F, Jiang D J, Xiong J, et al. A survey of phase change memory systems[J]. Journal of Computer Science and Technology, 2015, 30(1): 121-144.

[20] Zhang M, Zhang L, Lei J, et al. Quick-and-Dirty: Improving Performance of MLC PCM by Using Temporary Short Writes[C]// 2017 IEEE 35th International Conference on Computer Design. IEEE, 2017: 585-588.

[21] Song S, Das A, Mutlu O, et al. Improving phase change memory performance with data content aware access[C]//Proceedings of the 2020 ACM SIGPLAN International Symposium on Memory Management. 2020: 30-47.

[22] Kultursay E, Kandemir M, Sivasubramaniam A, et al. Evaluating STT-RAM as an energy-efficient main memory alternative[C]// 2013 IEEE International Symposium on Performance Analysis of Systems and Software. IEEE, 2013: 256–267.

[23] Rai S, Talawar B. Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems[J]. IETE Technical Review, 2022: 1-23.

[24] Akinaga H, Shima H. Resistive Random Access Memory (ReRAM) Based on Metal Oxides[J]. Proceedings of the IEEE, 2011, 98(12): 2237-2251.

[25] Mikolajick T, Dehm C, Hartner W, et al. FeRAM technology for high density applications[J]. Microelectronics Reliability, 2001, 41(7): 947-950.

[26] Alameldeen A R, Wood D A. Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches[J]. Technical report, University of Wisconsin-Madison Department of Computer Sciences, 2004.

[27] Pekhimenko G, Seshadri V, Mutlu O, et al. Base-delta-immediate compression: Practical data compression for on-chip caches[C]//Proceedings of the 21st international conference on Parallel architectures and compilation techniques. IEEE, 2012: 377–388.

[28] Angerd A, Arelakis A, Spiliopoulos V, et al. GBDI: Going beyond base-delta-immediate compression with global bases[C]//Proceedings of the 2022 IEEE International Symposium on High-Performance Computer Architecture.IEEE, 2022: 1115–1127.

[29] Yang J, Zhang Y, Gupta R. Frequent value compression in data caches[C]// IEEE/ACM International Symposium on Microarchitecture. IEEE, 2000: 258–265.

[30] Zhang Y, Yang J, Gupta R. Frequent value locality and value-centric data cache design[J]. ACM SIGARCH Computer Architecture News, 2000, 28(5): 150-159.

[31] Yang B D, Lee J E, Kim J S, et al. A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme[C]// IEEE International Symposium on Circuits & Systems. IEEE, 2007: 3014–3017.

[32] Liu H, Ye Y, Liao X, et al. Space-oblivious compression and wear leveling for non-volatile main memories[C]//Proc. the 36th International Conference on Massive Storage Systems and Technology. 2020.

[33] Nath A, Kapoor H K. WELCOMF: wear leveling assisted compression using frequent words in non-volatile main memories[C]//Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design. 2020: 157-162.

[34] Nath A, Kapoor H K. SWEL-COFAE: Wear Leveling and Adaptive Encoding Assisted Compression of Frequent Words in Non-Volatile Main Memories[J]. IEEE Transactions on Computers, 2021.71(9): 2263-2276.

[35] Dgien D B, Palangappa P M, Hunter N A, et al. Compression architecture for bit-write reduction in non-volatile memory technologies[C]//Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures. 2014: 51-56.

[36] Wang J, Dong X, Xie Y, et al. i2WAP: Improving non-volatile cache lifetime by reducing inter-and intra-set write variations[C]//2013 IEEE 19th International Symposium on High Performance Computer Architecture. IEEE, 2013: 234-245.

[37] Huang K, Mei Y, Huang L. Quail: Using NVM write monitor to enable transparent wear-leveling[J]. Journal of Systems Architecture, 2020, 102: 101658.

[38] Hakert C, Chen K H, Schirmeier H, et al. Software-managed read and write wear-leveling for non-volatile main memory[J]. ACM Transactions on Embedded Computing Systems, 2022, 21(1): 1-24.

[39] Xiao C, Cheng L, Zhang L, et al. Wear-aware Memory Management Scheme for Balancing Lifetime and Performance of Multiple NVM Slots[C]//2019 35th Symposium on Mass Storage Systems and Technologies. IEEE, 2019: 148-160.

[40] Qureshi M K, Karidis J, Franceschini M, et al. Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling[C]//Proceedings of the 42nd annual IEEE/ACM international symposium on microarchitecture. 2009: 14-23.

[41] Hakert C, Kühn R, Chen K H, et al. Octo+: Optimized checkpointing of b+ trees for non-volatile main memory wear-leveling[C]//2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium. IEEE, 2021: 1-6.

[42] Kulandai A D R, Rose J, Schwarz T. Balanced Gray Codes for Reduction of Bit-Flips in Phase Change Memories[C]//Modelling, Analysis, and Simulation of Computer and Telecommunication Systems: 28th International Symposium, MASCOTS 2020, Nice, France, November 17–19, 2020, Revised Selected Papers 28. Springer International Publishing, 2021: 159-171.

[43] Huang J, Peng M, Wu L, et al. Lamina: low overhead wear leveling for NVM with bounded tail[C]//2022 27th Asia and South Pacific Design Automation Conference. IEEE, 2022: 377-382.

[44] Bittman D, Long D D E, Alvaro P, et al. Optimizing Systems for Byte-Addressable NVM by Reducing Bit Flipping[C]// Proceedings of the 17th USENIX Conference on File and Storage Technologies, 2019:17–30.

[45] Bittman D, Gray M, Raizes J, et al. Designing data structures to minimize bit flips on NVM[C]//2018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium. IEEE, 2018: 85-90.

[46] Chen Y S, Wu C F, Chang Y H, et al. A write-friendly arithmetic coding scheme for achieving energy-efficient non-volatile memory systems[C]//Proceedings of the 26th Asia and South Pacific Design Automation Conference. 2021: 633-638.

[47] Cho S, Lee H. Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance[C]//Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture. 2009: 347-357.

[48] Alsuwaiyan A, Mohanram K. MFNW: An MLC/TLC Flip-N-Write Architecture[J]. ACM Journal on Emerging Technologies in Computing Systems, 2018, 14(2): 1-32.

[49] Jacobvitz A N, Calderbank R, Sorin D J. Coset coding to extend the lifetime of memory[C]//2013 IEEE 19th International Symposium on High Performance Computer Architecture. IEEE, 2013: 222-233.

[50] Kargar S, Nawab F. Hamming Tree: The Case for Memory-Aware Bit Flipping Reduction for NVM Indexing[C]// Conference on Innovative Data Systems Research. 2021.

[51] Kargar S, Litz H, Nawab F. Predict and write: Using k-means clustering to extend the lifetime of nvm storage[C]//2021 IEEE 37th International Conference on Data Engineering. IEEE, 2021: 768-779.

[52] Ho C C, Wang W C, Hsu T H, et al. Approximate programming design for enhancing energy, endurance and performance of neural network training on nvm-based systems[C]//2021 IEEE 10th Non-Volatile Memory Systems and Applications Symposium. IEEE, 2021: 1-6.

[53] Nath A, Kapoor H K. CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main Memories[C]//Proceedings of the Great Lakes Symposium on VLSI 2022. 2022: 393-396.

[54] Nath A, Kapoor H K. CADEN: Compression Assisted ADaptive Encoding to improve lifetime of Encrypted Non-Volatile Main Memories[J]. IEEE Embedded Systems Letters, 2022: 45-48.

[55] Wu S, Wu J, Shen Z, et al. SimiEncode: A Similarity-based Encoding Scheme to Improve Performance and Lifetime of Non-Volatile Main Memory[C]//2021 IEEE 39th International Conference on Computer Design. IEEE, 2021: 220-227.

[56] Ni Y, Zhao J, Bittman D, et al. Reducing NVM Writes with Optimized Shadow Paging[C]//10th USENIX Workshop on Hot Topics in Storage and File Systems. 2018: 22-22

[57] García A A, de Jong R, Wang W, et al. Composing lifetime enhancing techniques for non-volatile main memories[C]//Proceedings of the International Symposium on Memory Systems. 2017: 363-373.

[58] Binkert N, Beckmann B, Black G, et al. The gem5 simulator[J]. ACM SIGARCH computer architecture news, 2011, 39(2): 1-7.

[59] Poremba M, Xie Y. Nvmain: An architectural-level main memory simulator for emerging non-volatile memories[C]//2012 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2012: 392-397.

[60] Poremba M, Zhang T, Xie Y. Nvmain 2.0: A user-friendly memory simulator to model (non-) volatile memory systems[J]. IEEE Computer Architecture Letters, 2015, 14(2): 140-143.

[61] Ernesto V s O, Fernando Z, Ricco V C S. Benchmark Usando Gem5[EB/OL].[2021-11-20]. https://github.com/ernestovaz/gem5benchmarkcodes.

[62] Liu S, Seemakhupt K, Pekhimenko G, et al. Janus: Optimizing memory and storage support for non-volatile memory systems[C]//Proceedings of the 46th International Symposium on Computer Architecture. 2019: 143-156.

[63] Simo N, Antoni W, Markku M, et al. Telecom application transaction processing benchmark[EB/OL]. [2021-11-23]. http://tatpbenchmark. sourceforge.net/.

[64] Transaction Processing Performance Council (TPC)). TPC-C[EB/OL]. [2021-11-25]. http://www.tpc.org/tpcc/default.asp.

[65] Dadzie T H, Lee J, Kim J, et al. NVM-Shelf: Secure Hybrid Encryption with Less Flip for Non-Volatile Memory[J]. Electronics, 2020, 9(8): 1-27.

[66] Guo Y, Hua Y, Zuo P. DFPC: A dynamic frequent pattern compression scheme in NVM-based main memory[C]//2018 Design, Automation & Test in Europe Conference & Exhibition. IEEE, 2018: 1622-1627.